1. Field of the Invention
This invention relates generally to integrated circuit semiconducting devices and, more particularly, to high density semiconductor storage devices. The high density storage devices typically include redundant elements to replace defective elements which would compromise the integrity of the data signals stored therein.
2. Description of the Related Art
As integrated circuit semiconductor devices have become increasing complex while simultaneously including an increasing density of elements, the problem of fabricating a defect-free device has become increasing difficult. Although the probability of each element of a device being marginal or defective is extremely small, the enormous number of elements comprising each device has resulted in device fabrication yields which limit the commercial viability of the fabrication process. In order to increase the yields of the device fabrication process, redundant elements have been included in each device along with apparatus for replacing defective circuit elements with redundant circuit elements. Thus, if during the testing phase, an element is found to be defective, then the electrical paths to the defective element are disabled, and the electrical paths to the equivalent redundant element are enabled. Thereafter, the redundant element provides the functionality that could not be provided by the marginal or defective element.
By way of example, in integrated circuit semiconductor storage devices, the individual storage cells are arranged in a matrix array. The row or x-select apparatus enables a row of memory cells, while the column or y-select apparatus provides the address or access to a specific storage cell associated with the enabled storage cell row. The result of this addressing scheme is that a specific storage cell in the array of storage cells can be accessed in response to a preselected (address) signal group. When a storage cell of a matrix array column is found to be defective, a column of redundant storage cells is substituted for the original group of storage memory cells and a storage cell of the redundant column is accessed when the preselected signal group is applied to the storage device.
Referring to FIG. 1, a block diagram for the accessing of normal columns and for the accessing of redundant columns according to the related art is shown. Normal column address decoding circuit 11 and redundant column address detection circuit 16 have address signal groups identifying the column including the storage cell, which is to be accessed, applied thereto. Signals identifying a particular column generated by the redundant column address detection circuit 16 are applied to the redundant column decoder/driver unit 17. In addition, the redundant column address detection circuit 16 applies an ENABLE/DISABLE signal to the redundant column decoder/driver unit 17 and to the normal column decoder/driver unit 12. The normal column decoder/driver unit 12 applies an activating signal to the normal column conducting path, to which the storage cell being addressed is coupled. The redundant column decoder/driver unit applies signals to the redundant column conducting path activating a redundant column to which is coupled the storage cell identified by the address signals.
The operation of the column address apparatus of FIG. 1 can be understood as follows. In the absence of a defect in the storage cells which can be activated by column address decoding circuit 11 and the normal column decoder/driver unit 12, the ENABLE/DISABLE signal continuously disables redundant column decoder/driver unit 17 and continuously enables the normal column decoder/driver unit 12. Therefore, in the absence of a defective storage cell in the column conducting path to be accessed, the column conducting path to be activated is determined by the column address decoding circuits 11 and the normal column decoder/driver unit 12 in response to the column address signals. When, however, a defect in a storage cell coupled to a normal column conducting path is identified, then a non-defective redundant column conducting path is identified. The redundant column address detection circuits 16 is programmed, by means of a laser-activated fuse elements in the preferred embodiment, to respond to the address signal groups identifying the normal column with the identified address. As a result of the programming, when the column address signals are applied to the column address decoding circuit 11 and to the redundant column address detection circuit 16, the redundant column address detection circuits 16, by means of a change in the ENABLE/DISABLE signal, disables the normal column decoder/driver unit 12 thereby preventing activation of the defective normal column conducting path. The change in the ENABLE/DISABLE signal simultaneously enables the redundant column decoder/driver unit 17 so that the address signals applied to the redundant column address detection circuit 16 result in an activation signal being applied to the (now) enabled redundant column decoder/driver unit 17. As a result, an activation signal is applied to and activates the non-defective redundant column conducting path to which the storage cell to be addressed is coupled. In summary, as a result of programming the redundant column address detection circuit 16, the applied address signal groups activate a redundant column conducting path to which a non-defective storage cell is coupled, rather than activating the normal column conducting path to which a defective storage cell is coupled.
Referring next to FIG. 2, a partial schematic diagram for the redundant and normal column decoder/driver units 17 and 12, respectively, according to the preferred embodiment, is shown. Redundant column address detection circuit 16 applies address-derived signals to input terminals of logic NAND gates 172 through 174, these logic NAND gates being a part of redundant column decoder/driver unit 17. The ENABLE/DISABLE signal is applied to an input terminal of inverting amplifier 171. The output terminal of inverting amplifier 171 is coupled to an input terminal of each of logic NAND gates 172 through 174. The output terminals of logic NAND gates 172 through 174 are coupled to input terminals of inverting amplifiers 175 through 177, respectively. The output terminal of each inverting amplifier 175 through 177 is coupled to a redundant column conducting path. Address-derived signals from normal column address decoding circuit 11 are applied to a series of logic NAND gates 121a1 through 121n1, each logic NAND gate 121a1 through 121n1 being included in a normal column decoder/driver subunit 121a through 121n. Each logic NAND gate 121a1 through 121n1 has the ENABLE/DISABLE signal applied to an input terminal thereof. The output terminal of logic NAND gates 121a1 through 121n1 are applied input terminals of inverting amplifiers 121a2 through 121n2 respectively. The output signals of the inverting amplifiers 121a2 through 121n2 is applied to a multiplicity of normal column decoder/driver subunits. For example, the output signal from inverting amplifier 121a2 is applied to an input terminal of logic NAND gates 123b1 through 123n1, logic NAND gates 123b1 through 123n1 being included in normal column decoder/driver subunits 123b through 123n respectively. Using subunit 123b as an example, the output signal from logic NAND gate 123b1 is coupled through inverting amplifier 123b2, through inverting amplifier 123b3, and through inverting amplifier 123b4 to a normal column conducting path associated with a predetermined column address signal group. The operation of the apparatus shown in FIG. 2 follows the description for FIG. 1 except that preferred embodiment of the circuit implementation is shown. In the typical embodiment, the normal decoder/driver unit 12 drives 256 column conducting paths by activating, in response to address-derived signals, one of thirty-two output terminals for the normal column decoder/driver subunit 12a. The output terminals of the normal column decoder/driver subunit 12a can activate one of two hundred and fifty-six circuits in subunit 12b. For a given column address, the ENABLE/DISABLE signal determines whether a normal column conducting path is selected or a redundant column conducting path by controlling the operation of the NAND gates 172 through 174 and 121a1 through 121n1. The three series-coupled inverting amplifiers in the subunits of 12B (for example, 123b2, 123b3, and 123b4 provide a buffering to drive the (heavily loaded) columns of storage cells through a relatively small input signal. Furthermore, FIG. 2 suggests that, following the activation of the ENABLE/DISABLE signal, a six gate delay exists in the normal column decoder/driver unit 12, while a three gate delay is present in the redundant column decoder/driver unit 17.
The performance, and therefore the competitiveness, of the memory device should be maintained as the redundant elements are added. However, as indicated above, to avoid an overlap of activated column conducting paths, the activation of a redundant column conducting path following a normal column conducting path activation must be delayed because of the gate delay following the ENABLE/DISABLE signal.
A need has therefore been felt for a technique for disabling the activation of a normal column conducting path and enabling the activation a redundant column conducting path in a semiconducting memory without serious compromise in performance and without a difference in the delay times following the change in state of the ENABLE/DISABLE signal.